1. Field of the Invention
The invention relates to an information processing apparatus in which a plurality of units each comprising a semiconductor integrated circuit which operates on the basis of a system clock are arranged on a board and, more particularly, to an information processing apparatus in which a phase and a pulse width of the system clock which are caused by a variation on manufacturing the units can be adjusted.
2. Description of the Related Arts
Hitherto, in the development of an information processing apparatus such as a server or the like, realization of high reliability, reduction in costs, and decrease in number of shipping steps are very important subjects. Among them, for the realization of the high reliability, it is necessary to execute sufficient logic verification, a test for the guarantee of the margin operation in a severe environment, and the like. For the realization of the cost reduction, it is necessary to suppress product costs by reducing various expenses such as development expenses, testing expenses, and the like. Further, in order to realize the decrease in number of shipping steps, it is necessary to reduce various steps such as developing steps, testing steps, and the like. In the development of such a conventional information processing apparatus, in order to reduce the development expenses and decrease the developing steps and the testing steps, a new information processing apparatus is developed by assembling a new unit into a part of the information processing apparatus which has already been manufactured as a product. In this case, an adjustment of a system clock is necessary for fully utilizing functions implemented in the existing units without damaging the functions.
FIGS. 1A and 1B are an example of a conventional information processing apparatus which is made operative by a system clock and shows a clock system. In FIGS. 1A and 1B, a first unit 202 and a second unit 204 manufactured as LSIs are installed on a system board 200. For example, the second unit 204 is a processor and the first unit 202 is a control logic of the second unit. A system PLL circuit 206 as a system clock generator is provided for the first unit 202 and supplies the system clock to the second unit 204. A PLL circuit 244 as a clock generator exclusively for the second unit is provided for the second unit 204.
A phase and a pulse width of the system clock from the system PLL 206 are adjusted by a chopping circuit 210 and phase/width adjusting circuits 212 and 214. After that, the adjusted system clock is sent as a reference clock to the PLL 244 of the second unit 204 by a board line 236 and, at the same time, the system clock is supplied to a clock control circuit 222 of the first unit 202 itself by a board line 238. The system clock from the system PLL 206 is inputted to a clock gate generating circuit 216 of the first unit 202. On the basis of a control instruction of the supply and stop of the system clock which is given by a logic control circuit unit (not shown), for example, if the system clock is a minus clock, a clock gate signal which changes at timing during a clock plus period is formed and its phase is adjusted by delay adjusting circuits 218 and 220. After that, the clock gate signal is supplied to a clock control circuit 246 of the second unit 204 by a board line 240 and, at the same time, it is supplied to the clock control circuit 222 of the first unit 202 itself by a board line 242.
The clock control circuit 222 of the first unit 202 supplies a clock for a gate whose supply and stop have been controlled by the clock gate signal to a clock tree circuit 224 for a gate and, at the same time, supplies the continuous system clocks to a free-run clock tree circuit 226. The clock tree circuit 224 for the gate constructs, for example, a distributing circuit of four stages by distributing buffers 228-1 to 228-4 and supplies a clock to a gate of a control circuit (not shown). In this example, gates 232-1 and 232-2 serving as distribution destinations of the distributing buffer 228-4 of the final stage are shown. The free-run clock tree circuit 226 also similarly constructs a distributing circuit of four stages by distributing buffers 230-1 to 230-4 and supplies a free-run clock to a gate of a control circuit (not shown). A gate 234 serving as a distribution destination of the distributing buffer 230-4 of the final stage is shown as an example.
The clock control circuit 246 of the second unit 204 supplies a clock for a PLL which is not stopped by the clock gate signal from the first unit 202 to a clock tree circuit 248 for a PLL, supplies the clock for the gate whose supply and stop have been controlled by the clock gate signal to a clock tree circuit 250 for a gate, and at the same time, supplies the continuous system clocks to a free-run clock tree circuit 252. The clock tree circuit 248 for the PLL, the clock tree circuit 250 for the gate, and the free-run clock tree circuit 252 are constructed by an arbitrary number of distribution stages in accordance with a control logic circuit serving as a clock supply destination. Gates 254, 256, and 258 of the final stages are shown as examples. It is assumed that in such a system clock system of the first unit 202 and the second unit 204, it is necessary that a phase relation between, for example, a clock 260 which is inputted to the gate 232-1 of the final stage in the clock tree circuit 224 for the gate of the first unit 202 and a clock 262 which is inputted to the gate 256 of the final stage in the clock tree circuit 250 for the gate of the second unit 204 is kept constant.
The second unit 204 has the PLL 244, the clock of the clock tree circuit 248 for the PLL corresponding to the clock 262 is fed back, and an automatic adjustment is made so as to make a phase of the clock coincide with that of the system clock. Therefore, it is sufficient that the adjustment of the phase relation with the clock 260 is made with respect to a clock 264. To adjust the phase relation between the clock 260 of the first unit 202 and the clock 264 of the second unit 204 so as to be constant, hitherto, a clock adjustment testing apparatus is used, the system clock is supplied to the system board 200, the phase relation between the clocks 260 and 264 is actually measured, and delay values of the phase/width adjusting circuits 212 and 214 and the delay adjusting circuits 218 and 220 provided in the first unit 202 are adjusted, respectively. (Refer to JP-A-2000-029561, JP-A-2000-347764, and JP-A-3-209511.)
However, in the adjustment of the system clock in the conventional information processing apparatus as mentioned above, since the clock adjustment testing apparatus is used, there is such a problem that expenses for testing facilities and a testing step are caused. In the conventional apparatus, as circuits for adjusting the phases until the clock 260 or 264 is obtained from the system PLL 206 as a clock oscillating source, for example, phase/width adjusting circuits 212 and 214 and the delay adjusting circuits 218 and 220 in the first unit 202 have to be provided and a total delay time of the clock increases. Thus, a phase fluctuation due to environmental conditions or the like increases and it becomes a factor of obstructing the margin guarantee.